Verification Interacting with Synthesis -- Users' Mailing List Archive
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Starting: Sat Aug 30 2003 - 16:08:05 MDT
Ending: Mon Apr 13 2009 - 09:23:35 MDT

• Re: hello Francisco Javier Torres Valle (Tue Jan 13 2004 - 18:51:45 MST)
  1. sealani.gif (14917 bytes)
• Re: hello wangc (Tue Jan 13 2004 - 19:05:59 MST)
  1. sealani.gif (14917 bytes)
• A problem with ltl-model-checking Fang Wang (Sat Mar 27 2004 - 08:26:05 MST)
  1. test.zip (19325 bytes)
• Incomprehensive error message Zaher S Andraus (Thu Apr 08 2004 - 21:39:25 MDT)
  1. pipelined_xor_for_vis.v (2674 bytes)
• compilation problem, and 2 general questions Zaher S Andraus (Sun Apr 11 2004 - 23:07:31 MDT)
  1. pipelined_xor_for_vis_flattened.v (4472 bytes)
• Problems in flatten_hierarchy Varun Varshney (Mon Apr 12 2004 - 08:42:00 MDT)
  1. microwave.v (1280 bytes)
• ReguIar US Bank verification of the accounts. U.S. Bank (Sun Jul 25 2004 - 15:30:25 MDT)
  1. anthropology.GIF (8633 bytes)
• when using Cudd_foreachCube to get a cube, what the order do the vars in cube follow, index or current level? Li, Lun (Tue Sep 07 2004 - 08:21:43 MDT)
  1. winmail.dat (4042 bytes)
• vis segfault, Cudd_bddPickOneMinterm Tobe Toben (Wed Sep 08 2004 - 13:16:33 MDT)
  1. vis_segf.tgz (69805 bytes)
• RE: I cannot read blif file Graeme Cunningham (Thu Oct 07 2004 - 09:48:40 MDT)
  1. winmail.dat (3396 bytes)
• RE: About Questions of functions ttransferring a MDD to BDD in VIS --what I really want to do. Li, Lun (Mon Oct 18 2004 - 07:45:01 MDT)
  1. winmail.dat (2815 bytes)
• Silly question about compilation Junkie Dolphin (Wed Feb 16 2005 - 13:22:54 MST)
  1. part (190 bytes)
• ...! junkie\.dolphin\_at_libero\.it (Wed Apr 13 2005 - 09:35:56 MDT)
  1. formule.ltl (3292 bytes)
  2. eseguiSegv (90 bytes)
  3. modulo_debug.v (3463 bytes)
• Re: vis problem Youngsik Kim (Sun Jun 26 2005 - 17:05:01 MDT)
  1. MS05.tar.gz (575534 bytes)
• Help on error "# BMC: SAT Solver failed, try again" when runing arbiter example Li, Lun (Fri Aug 26 2005 - 11:56:32 MDT)
  1. winmail.dat (3209 bytes)
• Is the SAT_ALL algorithm published in DAC'05 implemented in current VIS release? Li, Lun (Tue Aug 30 2005 - 09:18:43 MDT)
  1. winmail.dat (2649 bytes)
• VL2MV output Prasad AVSS (Sun Oct 30 2005 - 20:53:53 MST)
  1. fpu_dec.v (6421 bytes)
  2. library.v (3204 bytes)
• RE: vl2mv Andrew Burnside (Sat Nov 05 2005 - 02:35:31 MST)
  1. winmail.dat (6818 bytes)
• CHINACOM2006 First Call For Papers Yabin Ye (Thu Feb 09 2006 - 08:45:39 MST)
  1. CHINACOM_First_CFP.pdf (117492 bytes)
• core dump for collapse_child Kelvin Lwin (Tue Apr 25 2006 - 20:30:13 MDT)
  1. main.mv (505396 bytes)
• Conditional branch in Verilog generating wrong BDD in VIS Flavio M. De Paula (Fri Jun 02 2006 - 23:05:38 MDT)
  1. comp.v (822 bytes)
  2. comp.mv (25920 bytes)
  3. vis_output (10991 bytes)
• Re: Dealing with BLIF files Mohammad.R Kakoee (Wed Jun 28 2006 - 08:47:08 MDT)
  1. README.vis.txt (16131 bytes)
• POTENTIAL SPAM: Timely Buying 0pportunity for this SmallCap? AETR . pk kwzbxilx (Mon Sep 11 2006 - 01:25:25 MDT)
  1. SWVXZ.bmp (10452 bytes)
• segmentation fault vl2mv yg2153_at_columbia.edu (Mon Nov 27 2006 - 10:01:00 MST)
  1. controller_test.v (6968 bytes)
• POTENTIAL SPAM: Looking for perfect sex Charity Scott (Tue Feb 20 2007 - 18:22:22 MST)
  1. ihqtjmd.gif (3992 bytes)
• Can't VIS a simple Verilog Zaher S Andraus (Sun Mar 25 2007 - 09:56:48 MDT)
  1. design1.mv (198831 bytes)
  2. design1.v (2377 bytes)
• Re: Can't VIS a simple Verilog Andrea Fedeli (Tue Mar 27 2007 - 22:58:59 MDT)
  1. design4.tgz (6015 bytes)
• blif-mv to blif /counter example yongjian Li (Sun Nov 04 2007 - 01:42:41 MST)
  1. yongjian_Li_1_.vcf (507 bytes)
• vis for psl jguo_at_sei.ecnu.edu.cn (Mon Nov 05 2007 - 18:03:55 MST)
  1. ctlpsl.psl (61 bytes)
  2. trafficlight.v (3914 bytes)
• VIS ERROR -- NEED HELP !! Aritra Hazra (Tue Jun 10 2008 - 22:09:53 MDT)
  1. test2.v (8939 bytes)
  2. test2.ctl (167 bytes)
• Help !! VIS Error !! Aritra Hazra (Mon Jun 23 2008 - 10:23:14 MDT)
  1. pci_synchronizer_flop.v (5279 bytes)
  2. pci_sync_module.v (5605 bytes)
• Help !! VIS Error !! The hierarchy manager is empty. Read in design. Aritra Hazra (Tue Jun 24 2008 - 21:00:44 MDT)
  1. pci_target32_interface.v (37232 bytes)
  2. pci_pci_decoder.v (9487 bytes)
  3. pci_async_reset_flop.v (4644 bytes)
• Help !! VIS Error !! The hierarchy manager is empty. Read in design. Aritra Hazra (Tue Jun 24 2008 - 05:31:02 MDT)
  1. pci_target32_interface.v (37232 bytes)
  2. pci_pci_decoder.v (9487 bytes)
  3. pci_async_reset_flop.v (4644 bytes)
• Help !! VIS Error !! The hierarchy manager is empty. Read in design. Aritra Hazra (Tue Jun 24 2008 - 00:57:26 MDT)
  1. pci_target32_interface.v (37232 bytes)
  2. pci_pci_decoder.v (9487 bytes)
  3. pci_async_reset_flop.v (4644 bytes)
• Fw: Help !! VIS Error !! The hierarchy manager is empty. Read in design. Aritra Hazra (Fri Jun 27 2008 - 04:17:45 MDT)
  1. pci_target32_interface.v (37232 bytes)
  2. pci_pci_decoder.v (9487 bytes)
  3. pci_async_reset_flop.v (4644 bytes)
• VIS Error in doing BMC of LTL Formula... Help !! Aritra Hazra (Thu Jul 03 2008 - 02:59:17 MDT)
  1. s27_wrong.ltl (15 bytes)
  2. s27.v (1021 bytes)
  3. s27_correct.ltl (18 bytes)
• Latch inference in VIS for Verilog models Waseem Muhammad (Tue Aug 12 2008 - 06:10:54 MDT)
  1. adder.v (322 bytes)
• problem with init_verify Sumit Ahuja (Fri Apr 03 2009 - 17:22:53 MDT)
  1. newpipe.v (716 bytes)

Last message date: Mon Apr 13 2009 - 09:23:35 MDT
Archived on: Mon Apr 13 2009 - 09:23:38 MDT

427 messages sorted by: [ author ] [ date ] [ thread ] [ subject ]
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