`timescale 1ns/1ps

module pipe_example (output1, input1, input2, in_select, clk);
input[15:0] input1, input2;
output[17:0] output1;
input in_select, clk;

wire[15:0] input1_int, input2_int;
reg[16:0] addition1;
reg[17:0] power1;
reg[17:0] output1_int;

assign input1_int = input1;
assign input2_int = input2;
assign output1 = output1_int;

//write an initial block here to initialize all the variables
initial begin
addition1   = 17'd0;
power1	    = 18'd0;
output1_int = 18'd0;
end

always@(posedge clk)
begin
	output1_int <= power1;
end

always@(posedge clk)
begin
	if(in_select)
	begin
		addition1 <= input1_int + input2_int;
	end
end

always@(posedge clk)
begin
	power1 <= addition1 + addition1;
end

endmodule