module adder(A1,B1,sum,clk);
input[0:63] A1,B1;
input clk;
wire[0:63] A1,B1;
wire clk;

output[0:63] sum;
reg[0:63] sum;
reg[0:63] A,B;

   initial
    begin
      sum = 64'b0;
      A = 64'b0;
      B = 64'b0;
    end

   always @(posedge clk)
    begin
      A = A1;
      B = B1;
      sum = A + B;
    end

endmodule