/*module main(clk);
  input clk;
  wire   [2:0] ns_light;  // North/South light status, Main road
  wire   [2:0]   ew_light;  // East/West light status
  wire 		   ew_sensor; // East/West sensor for new car
  wire  	   emgcy_sensor; // emergency sensor 
  wire  	   reset_n;   // synchronous reset
  
    
  trafficlight trafficlight(/*AUTOINST*/
							// Outputs
							.ns_light	(ns_light[2:0]),
							.ew_light	(ew_light[2:0]),
							// Inputs
							.ew_sensor	(ew_sensor),
							.emgcy_sensor(emgcy_sensor),
							.reset_n	(reset_n),
							.clk		(clk));
  
endmodule // tb
*/


module trafficlight
  (
   ns_light      , // North/South light status, Main road
   ew_light      , // East/West light status
   ew_sensor     , // East/West sensor for new car
   emgcy_sensor  , // emergency sensor 
   
   clk            // master clock
   );
  parameter FAIL   = 1'b0;
  
  parameter OFF       = 3'b000;
  parameter RED       = 3'b001;
  parameter YELLOW    = 3'b010;
  parameter GREEN     = 3'b011;
  parameter PRE_GREEN = 3'b100;
  

  


  
  
  output  [2:0] ns_light;  // North/South light status, Main road
  output  [2:0] ew_light;  // East/West light status
  input 	   ew_sensor; // East/West sensor for new car
  input 	   emgcy_sensor; // emergency sensor 
 
  input 	   clk;       // master clock
  
  reg [1:0]    ns_green_timer;  // timer for NS light in Green
  reg [1:0]    ew_green_timer;  // timer for EW light in GREEN
  wire [1:0] ns_light;  // North/South light status, Main road
  wire [1:0] ew_light;  // East/West light status
  
  
  reg [2:0]    ns_state  ;   // register that holds the current state of the FSM
  reg [2:0]    next_ns_state ; // register that holds the next state of the FSM 
  reg [2:0]    ew_state  ;   // register that holds the current state of the FSM
  reg [2:0]    next_ew_state ; // register that holds the next state of the FSM 
  
initial begin
	ns_green_timer=2'b00;
	ew_green_timer=2'b00;
	ns_state=OFF;
	ew_state=OFF;
	next_ns_state=OFF;
	next_ew_state=OFF;
  end
/*
  // North South FSM 
  always @ ( posedge clk )
	if (reset_n==1'b0) ns_state = OFF;
	else  ns_state <= next_ns_state;

   // East West  FSM 
  always @ ( posedge clk )
	if (reset_n==1'b0) ew_state = OFF;
	else  ew_state <= next_ew_state;
*/
  // NS FSM machine 
  always @ (posedge clk)
	begin 
	  next_ns_state = ns_state; // default
      case (ns_state)
		OFF   : next_ns_state = GREEN;
		RED   : 
		 //  if (emgcy_sensor==1'b0 && ew_green_timer==2'b11)
		 //	next_ns_state= GREEN; // Error // priority to North South
		  if (ew_green_timer==3'b11) next_ns_state=GREEN;
		YELLOW: next_ns_state=RED;
		GREEN :
		  if (emgcy_sensor==1'b1) next_ns_state=YELLOW;
		  else if (ns_green_timer==2'b11 && ew_sensor==1'b1) next_ns_state=YELLOW;
		default: next_ns_state= ns_state;
      endcase
	end
  
  // EW FSM machine 
  always @ (posedge clk)
	begin 
	  next_ew_state = ew_state; // default
      case (ew_state)
		OFF   : next_ew_state = RED;
		RED   : 
		  if (ns_green_timer==3'b11 && ew_sensor==1'b1) next_ew_state=PRE_GREEN;
		PRE_GREEN : next_ew_state = GREEN;
		YELLOW: next_ew_state=RED;
		GREEN :
		  if (emgcy_sensor==1'b1) next_ew_state=YELLOW;
		  else if (ew_green_timer==2'b11) next_ew_state=YELLOW;
      endcase
	end
  
  // NS Counter
  // ** fix, need to latch counter to 3 
   always @ ( posedge clk )
	 if (ns_state==YELLOW)   ns_green_timer = 2'b00;
	 else if (ns_green_timer != 2'b11) ns_green_timer = ns_green_timer + 2'b01;
    

  // EW Counter
   always @ ( posedge clk )
	 if (ew_state==YELLOW)   ew_green_timer = 2'b00;
     // Bad assumption here 
	 else if (ns_state==RED) ew_green_timer= ew_green_timer + 2'b01;

  assign ns_light = ns_state;

  assign ew_light = (ew_state==PRE_GREEN) ? RED : ew_state;
  
endmodule  //