module design1(d1,d2,d3,d4,clk,sres1,sres2,sres3,sres4,ires1,ires2,ires3,ires4);
   input clk;

   input [14:0] d1;   
   input [14:0] d2;   
   input [14:0] d3;   
   input [14:0] d4;   

   output [14:0] sres1;
   output [14:0] sres2;
   output [14:0] sres3;
   output [14:0] sres4;
   output [14:0] ires1;
   output [14:0] ires2;
   output [14:0] ires3;
   output [14:0] ires4;   
   
   reg [14:0]   s11;
   reg [14:0]   s12;   
   reg [14:0]   s13;   
   reg [14:0]   s14;
   reg [14:0]   s21;
   reg [14:0]   s22;
   reg [14:0]   s23;
   reg [14:0]   s24;
   reg [14:0]   sres1;
   reg [14:0]   sres2;
   reg [14:0]   sres3;
   reg [14:0]   sres4;

   reg [14:0]   i11;
   reg [14:0]   i12;   
   reg [14:0]   i13;   
   reg [14:0]   i14;
   reg [14:0]   i21;
   reg [14:0]   i22;
   reg [14:0]   i23;
   reg [14:0]   i24;
   reg [14:0]   ires1;
   reg [14:0]   ires2;
   reg [14:0]   ires3;
   reg [14:0]   ires4;

   // Implementation
   
   always @(posedge clk)
     s11 <= d1>d2?d1:d2;
   always @(posedge clk)
     s12 <= d1>d2?d2:d1;
   always @(posedge clk)
     s13 <= d3>d4?d3:d4;
   always @(posedge clk)
     s14 <= d3>d4?d4:d3;
   always @(posedge clk)
     s21 <= s11>s13?s11:s13;
   always @(posedge clk)
     s22 <= s11>s13?s13:s11;
   always @(posedge clk)
     s23 <= s12>s14?s12:s14;
   always @(posedge clk)
     s24 <= s12>s14?s14:s12;
   always @(posedge clk)
     sres1 <= s21;
   always @(posedge clk)
     sres2 <= s22>s23?s22:s23;
   always @(posedge clk)
     sres3 <= s22>s23?s23:s22;
   always @(posedge clk)
     sres4 <= s24;
   
   // Specification (unfolded already!)
   
   always @(posedge clk)
     i11 <= d1>d2?d1:d2;
   always @(posedge clk)
     i12 <= d1>d2?d2:d1;
   always @(posedge clk)
     i13 <= d3>d4?d3:d4;
   always @(posedge clk)
     i14 <= d3>d4?d4:d3;
   always @(posedge clk)
     i21 <= i11>i13?i11:i13;
   always @(posedge clk)
     i22 <= i11>i13?i13:i11;
   always @(posedge clk)
     i23 <= i12>i14?i12:i14;
   always @(posedge clk)
     i24 <= i12>i14?i14:i12;
   always @(posedge clk)
     ires1 <= i21>i24?i21:i24;   
   always @(posedge clk)
     ires2 <= i22>i23?i22:i23;
   always @(posedge clk)
     ires3 <= i22>i23?i23:i22;
   always @(posedge clk)
     ires4 <= i21>i24?i24:i21;
   
endmodule // design1