/************* Encoded Muxes *************/


module mj_p_mux2 (
    mx_out, 
    in1,
    in0,
    sel,
    sel_l ) ;

    output mx_out;
    input in1;
    input in0;
    input sel;
    input sel_l;


reg mx_out;

always @(sel or in1 or in0 )
begin  
    case (sel)
    1'b1: mx_out = in1;
    1'b0: mx_out = in0;
    default: mx_out = 1'bx;
    endcase 
end 

endmodule

module mj_s_mux2_d_8 (mx_out, sel, in0, in1);

output [7:0] mx_out;
input    sel;
input  [7:0]  in0 , in1 ;
/*
wire    sel_not, mux_sel;
assign sel_not = ~sel;
assign mux_sel =  sel;
assign mx_out  = (mux_sel & in1 | sel_not & in0) ;
*/

wire selb;
wire sel1;
wire sel1b;

assign selb = ~sel;
assign sel1 = ~selb;
assign sel1b = ~sel1;


mj_p_mux2_8  mj_p_mux2_8_0 (
    		.mx_out(mx_out), 
    		.in1(in1),
    		.in0(in0),
    		.sel(sel1) ,
		.sel_l(sel1b)) ;
endmodule



module mj_p_mux2_8 (mx_out, in1, in0, sel, sel_l);
    output [7:0] mx_out;
    input  [7:0] in1; 
    input  [7:0] in0; 
    input    sel ; input  sel_l;

    mj_p_mux2  mux_0 (.mx_out(mx_out[0]), .in1(in1[0]), .in0(in0[0]), .sel(sel), .sel_l(sel_l));
    mj_p_mux2  mux_1 (.mx_out(mx_out[1]), .in1(in1[1]), .in0(in0[1]), .sel(sel), .sel_l(sel_l));
    mj_p_mux2  mux_2 (.mx_out(mx_out[2]), .in1(in1[2]), .in0(in0[2]), .sel(sel), .sel_l(sel_l));
    mj_p_mux2  mux_3 (.mx_out(mx_out[3]), .in1(in1[3]), .in0(in0[3]), .sel(sel), .sel_l(sel_l));
    mj_p_mux2  mux_4 (.mx_out(mx_out[4]), .in1(in1[4]), .in0(in0[4]), .sel(sel), .sel_l(sel_l));
    mj_p_mux2  mux_5 (.mx_out(mx_out[5]), .in1(in1[5]), .in0(in0[5]), .sel(sel), .sel_l(sel_l));
    mj_p_mux2  mux_6 (.mx_out(mx_out[6]), .in1(in1[6]), .in0(in0[6]), .sel(sel), .sel_l(sel_l));
    mj_p_mux2  mux_7 (.mx_out(mx_out[7]), .in1(in1[7]), .in0(in0[7]), .sel(sel), .sel_l(sel_l));

endmodule 



module mj_s_ff_snre_d_8 (out, din, lenable, reset_l,clk);
    output  [7:0]  out;
    input   [7:0]  din;
    input           lenable;
    input           clk;
    input           reset_l;

    mj_s_ff_snre_d    mj_s_ff_snre_d_0(.out(out[0]), .in(din[0]), .lenable(lenable), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snre_d    mj_s_ff_snre_d_1(.out(out[1]), .in(din[1]), .lenable(lenable), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snre_d    mj_s_ff_snre_d_2(.out(out[2]), .in(din[2]), .lenable(lenable), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snre_d    mj_s_ff_snre_d_3(.out(out[3]), .in(din[3]), .lenable(lenable), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snre_d    mj_s_ff_snre_d_4(.out(out[4]), .in(din[4]), .lenable(lenable), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snre_d    mj_s_ff_snre_d_5(.out(out[5]), .in(din[5]), .lenable(lenable), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snre_d    mj_s_ff_snre_d_6(.out(out[6]), .in(din[6]), .lenable(lenable), .reset_l(reset_l),.clk(clk));
    mj_s_ff_snre_d    mj_s_ff_snre_d_7(.out(out[7]), .in(din[7]), .lenable(lenable), .reset_l(reset_l),.clk(clk));

endmodule 



module mj_s_ff_snre_d(out,in, lenable,reset_l, clk);
output out;
input clk;
input lenable;
input reset_l;
input in;

reg out;
always @(posedge clk)
        if (~reset_l) 
	out <= 1'b0;
	else
    	if (lenable)
            out <= in;
        else
            out <= out;

endmodule