module top();

wire [31:0] impl_pc;
reg [31:0] impl_mem[1:0];

wire [31:0] impl_pc_new;
reg [31:0] impl_mem_new[1:0];

wire spec_proj;
reg [4:0] cnt;
wire spec_flush;
wire impl_flush;

wire one;
assign one = 1'b1;
// start of module: impl impl_old_mod

wire clk;

wire one;



reg [31:0] impl_pc;
reg _impl_old_mod__stall;

reg [31:0] _impl_old_mod__InstMem[1:0];

initial
   begin
 _impl_old_mod__InstMem[0] = 0;
 _impl_old_mod__InstMem[1] = 0;
 impl_mem[0] = 0;
 impl_mem[1] = 0;
 impl_pc_saved = 0;
 _impl_old_mod__memout_saved = 0;
 impl_pc = 0;

 _impl_old_mod__stall = 1'b0;
 _impl_old_mod__stall_saved = 1'b0;

 cnt = 0;

 _spec_mod__InstMem[0] = 0;
 _spec_mod__InstMem[1] = 0;
 _spec_mod__DataMem[0] = 0;
 _spec_mod__DataMem[1] = 0;
 _spec_mod__pc = 0;
 _spec_mod__spec_stall = 0;

 _impl_new__InstMem[0] = 0;
 _impl_new__InstMem[1] = 0;
 impl_mem_new[0] = 0;
 impl_mem_new[1] = 0;
 impl_pc_new_saved = 0;
 _impl_new__memout_saved = 0;
 impl_pc_new = 0;

 _impl_new__stall = 1'b0;
 _impl_new__stall_saved = 1'b0;
end

wire [31:0] _impl_old_mod__memout;
assign _impl_old_mod__memout = _impl_old_mod__InstMem[impl_pc[0:0]];

always @(posedge clk)
 if(_impl_old_mod__wr_en)
//  impl_mem[impl_pc[0:0]] = _impl_old_mod__res;
  impl_mem[0] = _impl_old_mod__res;

reg [31:0] impl_pc_saved;
reg [31:0] _impl_old_mod__memout_saved;
reg _impl_old_mod__stall_saved;

always @(posedge clk) begin
 impl_pc_saved <= impl_pc;
 _impl_old_mod__memout_saved <= _impl_old_mod__memout;
 _impl_old_mod__stall_saved <= _impl_old_mod__stall;
end

wire [31:0] _impl_old_mod__res;
assign _impl_old_mod__res = _impl_old_mod__memout_saved & impl_pc_saved;

always @(posedge clk)
 if (!one)
  impl_pc <= impl_pc+1;



always @(posedge clk)
 if(one)
  _impl_old_mod__stall <= 1'b1;
 else
  _impl_old_mod__stall <= 1'b0;

wire _impl_old_mod__wr_en;
assign _impl_old_mod__wr_en = !_impl_old_mod__stall_saved;


// end of module: impl_old_mod




always @(posedge clk) begin
 cnt <= cnt + 1;
end

assign spec_proj = (cnt==2);

assign spec_flush = (cnt>=3);

wire impl_proj;
// start of module: spec spec_mod

wire clk;

wire spec_proj;

wire [31:0] impl_pc;

wire spec_flush;

reg [31:0] _spec_mod__pc;

reg [31:0] _spec_mod__InstMem[1:0];
reg [31:0] _spec_mod__DataMem[1:0];

integer _spec_mod__i;



wire [31:0] _spec_mod__memout;
assign _spec_mod__memout = _spec_mod__InstMem[_spec_mod__pc[0:0]];

reg _spec_mod__spec_stall;

always @(spec_proj)
if(spec_proj)
 _spec_mod__spec_stall = 1'b1;
else
 _spec_mod__spec_stall = 1'b0;

wire _spec_mod__spec_wr_en;
assign _spec_mod__spec_wr_en = !_spec_mod__spec_stall;

always @(posedge clk)
 if(spec_proj) begin
   _spec_mod__DataMem <= impl_mem;
 end
 else if(_spec_mod__spec_wr_en)
  _spec_mod__DataMem[_spec_mod__pc[0:0]] = _spec_mod__res;

wire [31:0] _spec_mod__res;
assign _spec_mod__res = _spec_mod__memout & _spec_mod__pc;

wire clk;

always @(posedge clk)
if(spec_proj)
 _spec_mod__pc <= impl_pc;
else if (spec_flush)
 _spec_mod__pc <= _spec_mod__pc;
else
 _spec_mod__pc <= _spec_mod__pc + 1;


// end of module: spec_mod


assign impl_flush = (cnt!=0);
// start of module: impl impl_new

wire clk;

wire impl_flush;



reg [31:0] impl_pc_new;
reg _impl_new__stall;

reg [31:0] _impl_new__InstMem[1:0];
reg [31:0] impl_mem_new[1:0];



wire [31:0] _impl_new__memout;
assign _impl_new__memout = _impl_new__InstMem[impl_pc_new[0:0]];

always @(posedge clk)
 if(_impl_new__wr_en)
  impl_mem_new[impl_pc_new[0:0]] = _impl_new__res;

reg [31:0] impl_pc_new_saved;
reg [31:0] _impl_new__memout_saved;
reg _impl_new__stall_saved;

always @(posedge clk) begin
 impl_pc_new_saved <= impl_pc_new;
 _impl_new__memout_saved <= _impl_new__memout;
 _impl_new__stall_saved <= _impl_new__stall;
end

wire [31:0] _impl_new__res;
assign _impl_new__res = _impl_new__memout_saved & impl_pc_new_saved;

always @(posedge clk)
 if (!impl_flush)
  impl_pc_new <= impl_pc_new+1;



always @(posedge clk)
 if(impl_flush)
  _impl_new__stall <= 1'b1;
 else
  _impl_new__stall <= 1'b0;

wire _impl_new__wr_en;
assign _impl_new__wr_en = !_impl_new__stall_saved;


// end of module: impl_new

wire eq;
assign eq = (cnt>=3) || ((impl_pc_new == impl_pc) && (impl_mem_new[0] == impl_mem[0]) && (impl_mem_new[1] == impl_mem[1]));

endmodule