module spec(clk,proj,impl_pc,flush,impl_mem);

input clk;
wire clk;

input proj;
wire proj;

input impl_pc;
wire [31:0] impl_pc;

input impl_mem;
reg [31:0] impl_mem[1:0];

input flush;
wire flush;

reg [31:0] pc;

reg [31:0] InstMem[1:0];
reg [31:0] DataMem[1:0];

integer i;

initial begin
 InstMem[0] = 0;
 InstMem[1] = 0;
 DataMem[0] = 0;
 DataMem[1] = 0;
 pc = 0;
 spec_stall = 0;
end

wire [31:0] memout;
assign memout = InstMem[pc[0:0]];

reg spec_stall;
//assign spec_stall = 1'b0;
always @(proj)
if(proj)
 spec_stall = 1'b1;
else
 spec_stall = 1'b0;

wire spec_wr_en;
assign spec_wr_en = !spec_stall;

always @(posedge clk)
 if(proj)
  DataMem <= impl_mem;
 else if(spec_wr_en)
  DataMem[pc[0:0]] = res;

wire [31:0] res;
assign res = memout & pc;

wire clk;

always @(posedge clk)
if(proj)
 pc <= impl_pc;
else if (flush)
 pc <= pc;
else
 pc <= pc + 1;

endmodule

module impl(clk,flush,pc,DataMem);

input clk;
wire clk;

input flush;
wire flush;

output pc;
output DataMem;

reg [31:0] pc;
reg stall;

reg [31:0] InstMem[1:0];
reg [31:0] DataMem[1:0];

initial begin
 InstMem[0] = 0;
 InstMem[1] = 0;
 DataMem[0] = 0;
 DataMem[1] = 0;
 pc_saved = 0;
 memout_saved = 0;
 pc = 0;
end

wire [31:0] memout;
assign memout = InstMem[pc[0:0]];

always @(posedge clk)
 if(wr_en)
  DataMem[pc[0:0]] = res;

reg [31:0] pc_saved;
reg [31:0] memout_saved;
reg stall_saved;

always @(posedge clk) begin
 pc_saved <= pc;
 memout_saved <= memout;
 stall_saved <= stall;
end

wire [31:0] res;
assign res = memout_saved & pc_saved;

always @(posedge clk)
 if (!flush)
  pc <= pc+1;

initial begin
 stall = 1'b0;
 stall_saved = 1'b0;
end

always @(posedge clk)
 if(flush)
  stall <= 1'b1;
 else
  stall <= 1'b0;

wire wr_en;
assign wr_en = !stall_saved;

endmodule
 
module top();

wire [31:0] impl_pc;
reg [31:0] impl_mem[1:0];

wire [31:0] impl_pc_new;
reg [31:0] impl_mem_new[1:0];

initial begin
 impl_mem[0] = 0;
 impl_mem[1] = 0;
 impl_mem_new[0] = 0;
 impl_mem_new[1] = 0; 
end

wire spec_proj;
reg [4:0] cnt;
wire spec_flush;
wire impl_flush;

impl impl_old_mod(1'b1,impl_pc,impl_mem);

initial begin
 cnt = 0;
end

always @(posedge clk) begin
 cnt <= cnt + 1;
end

assign spec_proj = (cnt==2);

assign spec_flush = (cnt>=3);

wire impl_proj;

spec spec_mod(clk,spec_proj,impl_pc,spec_flush,impl_mem);

assign impl_flush = (cnt!=0);

impl impl_new(clk,impl_flush,impl_pc_mew,impl_mem_new);

wire eq;
assign eq = (cnt>=3) || ((impl_pc_new == impl_pc) && (impl_mem_new == impl_mem));

endmodule