problem with init_verify

From: Sumit Ahuja (sahuja_at_vt.edu)
Date: Fri Apr 03 2009 - 17:22:53 MDT

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Hello All,

I am a beginner of vis and I tried running a small design and got few errors
during init_verify stage. I used read_verilog and it worked fine with one
warning. I am attaching the verilog along with this mail. I will appreciate
if somebody can point me to the error.

Here is how error looks like:

vis> init_verify

Table _nd<0> is not deterministic

Table _nd<1> is not deterministic

Table _nd<2> is not deterministic

Table _nd<3> is not deterministic

Table _nd<4> is not deterministic

Table _nd<5> is not deterministic

Table _nd<6> is not deterministic

Table _nd<7> is not deterministic

....

---
Sincerely,
Sumit Ahuja,
FERMAT Lab, Virginia Tech.
http://fermat.ece.vt.edu/Fermatian_Info/sumit.html
 
 

• application/octet-stream attachment: newpipe.v

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