Re: Latch inference in VIS for Verilog models (2)

From: Andrea Fedeli (andrea.fedeli_at_mclink.it)
Date: Fri Aug 15 2008 - 05:18:03 MDT

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Errata :) : s/A2/B1/ < [my_previous_email]

-- 
Andrea Fedeli
If you can't be good, be careful.  If you can't be careful, give me a
call.

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