From: Andrea Fedeli (andrea.fedeli_at_mclink.it)
Date: Fri Aug 15 2008 - 00:01:43 MDT
Hi Waseem:
Waseem Muhammad wrote:
> Hello,
> I have a simple 64-bit adder example in Verilog (attached). When I
> read in the design by VIS and check the network statistics
> (print_network_stat). It shows me 192 latches. Whereas actually there
> should be 64 latches as I see from the synthesis results obtained from
> Precision and Cadence synthesis tools. Does VIS represents all 'reg'
> type Verilog variables as latches no matter semantically they are
> hardware registers or not?
>
> 'Reg' variables 'A' and 'B' are not hardware registers because they
> are assigned by blocking statements but they are inferred as hardware
> registers by VIS. Is n't it a problem?
Your code should cause the inferring of 64*3 (SUM, A, B) latches, as
you're sampling, and producing, data just on rising edge of clock (so
ideally you should keep those value in all other moments in time). As a
matter of fact, though, A and B may be removed in SUM computation, as by
substitution you might use A1 and A2 directly. Commercial compilers can
take advantage of that substitution and reduce the count to 64.
-- Andrea Fedeli Horse sense is the thing a horse has which keeps it from betting on people. -- W. C. Fields
This archive was generated by hypermail 2.1.7 : Fri Aug 15 2008 - 00:03:44 MDT