Latch inference in VIS for Verilog models

From: Waseem Muhammad (Waseem.Muhammad_at_eurecom.fr)
Date: Tue Aug 12 2008 - 06:10:54 MDT

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Hello,
   I have a simple 64-bit adder example in Verilog (attached). When I
read in the design by VIS and check the network statistics
(print_network_stat). It shows me 192 latches. Whereas actually there
should be 64 latches as I see from the synthesis results obtained from
Precision and Cadence synthesis tools. Does VIS represents all 'reg'
type Verilog variables as latches no matter semantically they are
hardware registers or not?

'Reg' variables 'A' and 'B' are not hardware registers because they are
assigned by blocking statements but they are inferred as hardware
registers by VIS. Is n't it a problem?

Regards
Waseem

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Waseem MUHAMMAD
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