From: Aritra Hazra (aritrah_at_cse.iitkgp.ernet.in)
Date: Fri Jun 27 2008 - 04:17:45 MDT
Hello !!
When I am using VIS, I found that some verilog designs are
compiled properly (without errors) using "read_verilog"
-command, but then while running "init_verify"-command
(particularly "flatten_hierarchy"), they report an error as
follows:
"The hierarchy manager is empty. Read the design."
I am attaching one such example containing my three
verilog test files namely, "pci_target32_interface.v",
"pci_pci_decoder.v" and "pci_async_reset_flop.v".
"pci_target32_interface.v" file instantiates two modules
declared in "pci_pci_decoder.v" and
"pci_async_reset_flop.v". The error occurs only during
"init_verify" of the first file after "read_verilog".
It seems that VIS cannot build the hierarchy. Kindly suggest
that why such errors are happening even if my design
passes through successful compilation and how we can get
rid of it.
Thanking you for your time,
-----
Aritra Hazra.
MS Student & Research Consultant,
Department of Computer Science & Engineering,
Indian Institute of Technology, Kharagpur.
INDIA - 721302
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