Help !! VIS Error !! The hierarchy manager is empty. Read in design.

From: Aritra Hazra (aritrah_at_cse.iitkgp.ernet.in)
Date: Tue Jun 24 2008 - 21:00:44 MDT

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Hello !!

I am encountering an error while attempting to use
VIS for building flattened-hierarchy through
"init_verify"-command after compiling a verilog program
(pci_target32_interface.v).

The error message looks like:
The hierarchy manager is empty. Read in design.

I am attaching my three verilog test files namely,
"pci_target32_interface.v", "pci_pci_decoder.v" and
"pci_async_reset_flop.v".

"pci_target32_interface.v" file instantiates two modules
declared in "pci_pci_decoder.v" and
"pci_async_reset_flop.v". The error occurs only during
"init_verify" of the first file.

Kindly help me regarding this and suggest how I can get rid
of this error.

Thanking you for your time,
-----
Aritra Hazra.
MS Student & Research Consultant,
Department of Computer Science & Engineering,
Indian Institute of Technology, Kharagpur.
INDIA - 721302

• application/octet-stream attachment: pci_target32_interface.v

• application/octet-stream attachment: pci_pci_decoder.v

• application/octet-stream attachment: pci_async_reset_flop.v

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