From: Aritra Hazra (aritrah_at_cse.iitkgp.ernet.in)
Date: Mon Jun 23 2008 - 10:23:14 MDT
Sir,
I am encountering an error while attempting to use VIS to
compile a verilog program (pci_sync_module.v) by
"read_verilog"-command.
The error message looks like:
Error: Variable meta_del_bit is not defined as an
output of a table in model pci_sync_module.
I am attaching my two verilog test files namely,
"pci_sync_module.v" and "pci_synchronizer_flop.v".
"pci_sync_module.v" file instantiates a module declared in
"pci_synchronizer_flop.v". The second file has no
instantiation and it compiles correctly as individual, but error
occurs during compilation of the first.
Kindly help me regarding this and suggest how I can get rid
of this error.
Thanking you for your time,
-----
Aritra Hazra.
MS Student & Research Consultant,
Department of Computer Science & Engineering,
Indian Institute of Technology, Kharagpur.
INDIA - 721302
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