From: Aritra Hazra (aritrah_at_cse.iitkgp.ernet.in)
Date: Tue Jun 10 2008 - 22:09:53 MDT
Sir,
I am encountering an error while attempting to use VIS to
verify a simple "128-bit fulladder" file in verilog with a CTL file
having one CTL formula.
The error message looks like:
** mc error: error in parsing Atomic Formula:
Could not find node corresponding to the name
- fulladder128.a<127>
(Wire for this name may have been removed by synthesis)
I have seen few solutions to this error in:
(i) VIS FAQ page (point-8)
(http://vlsi.colorado.edu/~vis/doc/html/vis-faq.html) and
(ii) The mails regarding such problem in
http://vlsi.colorado.edu/~vis/vis-users2/0104.html.
But, approaching according to the previous two
suggestions do not help me either.
I am attaching my verilog test file and the CTL formula file.
Kindly help me regarding this and suggest how I can get rid
of this error.
Thanking you for your time,
-----
Aritra Hazra.
MS Student & Research Consultant,
Department of Computer Science & Engineering,
Indian Institute of Technology, Kharagpur.
INDIA - 721302
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