From: yongjian Li (lyj238_at_ios.ac.cn)
Date: Sun Nov 04 2007 - 01:42:41 MST
hi,
I'm a beginner in VIS.
Recently, I test the example in VIS/verilog.
The blif_mv of the counter is no problem, but the blif file generated
by vis is as follows, it is very strangeand I can not see the
relationship between the
blif file with the conter.bmv or counter.v.The problem is that I can
not use the counter.blif to
analyze a model to check the counter.ctl formula.
Could you please explain sth about it?
Could you please tell me what Vis has done in translating a blif_mv to
blif.
.model counter
.inputs
.outputs _n00
.names _n00
1
.exdc
.end
the source verilog file is as follows:
module counter(clk);
input clk;
wire out0, out1, out2;
counter_cell bit0 (clk, 1, out0);
counter_cell bit1 (clk, out0, out1);
counter_cell bit2 (clk, out1, out2);
endmodule
module counter_cell(clk, carry_in, carry_out);
input clk;
input carry_in;
output carry_out;
reg value;
assign carry_out = value & carry_in;
initial value = 0;
always @(posedge clk) begin
// value = (value + carry_in) % 2;
case(value)
0: value = carry_in;
1: if (carry_in ==0)
value = 1;
else value = 0;
endcase
end
endmodule
Yongjian Li
Laboratory of Computer Science
Institute of Software
Chinese Academy of Sciences
P.O.Box 8718, Beijing 100080
P.R. CHINA
Tel：86-10-62661658
Fax: 86-10-62661627
2007-11-04
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