Open cores in Verlilog synthesizable with vl2mv

From: Ashish Darbari (ad06v_at_ecs.soton.ac.uk)
Date: Wed Apr 04 2007 - 08:22:55 MDT

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Has anyone used vl2mv to generate a BLIF-MV netlist of a
micro-processor? Is there an
open-source IP core of such a micro-processor out there? I notice there
are quite a few Verilog
decsribed CPU cores on opencores.org, but am not sure which ones have
been known to work
with vl2mv. Any help is very much appreicated.

Ashish

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