From: Andrea Fedeli (andrea.fedeli_at_mclink.it)
Date: Tue Mar 27 2007 - 22:58:59 MDT
Hi Zaher:
Zaher S Andraus wrote:
> I ran vl2mv on the attached Verilog and got a valid mv file.
> Now in VIS, running flatten hierarchy or init_verify gives
> me the following errors...
> [...]
> Does anyone understand the reason behind this?
I've played a bit with your example and from the basic trials I've made
it seems to be a vl2mv issue; the generated translation presents pairs
of lines like
.names _n360 [...] -> _n363<0> [...]
.def - - - - - - - - - - - - - - -
for each of the reported "errors".
Replacing
.def - - - - - - - - - - - - - - -
with, for instance,
.def 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
the errors disappears.
I'm inclined toward a vl2mv issue as from the trials I've made, reducing
the arrays in your example to scalars and adding an initial block that
should have reasonably assigned 0 by default to all the intermediate
and output signals (cf. annex), the .def - is still there.
HTH.
Cheers,
Andrea.
-- Andrea Fedeli Disco is to music what Etch-A-Sketch is to art.
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