From: Zaher S Andraus (zandrawi_at_eecs.umich.edu)
Date: Sun Mar 25 2007 - 09:56:48 MDT
Hi,
I ran vl2mv on the attached Verilog and got a valid mv file.
Now in VIS, running flatten hierarchy or init_verify gives
me the following errors...
[ 48 ] design1 -: vis
vis release 2.0 (compiled 27-Sep-03 at 6:43 PM)
vis> read_blif_mv design1.mv
vis> init_verify
Table _n363<0> is not deterministic
Table _n363<1> is not deterministic
Table _n363<2> is not deterministic
Table _n363<3> is not deterministic
Table _n363<4> is not deterministic
Table _n363<5> is not deterministic
Table _n363<6> is not deterministic
Table _n363<7> is not deterministic
Table _n363<8> is not deterministic
Table _n363<9> is not deterministic
Table _n363<10> is not deterministic
Table _n363<11> is not deterministic
Table _n363<12> is not deterministic
Table _n363<13> is not deterministic
Table _n363<14> is not deterministic
Table _n369<0> is not deterministic
Table _n369<1> is not deterministic
...
etc.
Does anyone understand the reason behind this?
Thanks in advance,
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Zaher S. Andraus
Advanced Computer Architecture Laboratory in EECS
University of Michigan - Ann Arbor
http://www.eecs.umich.edu/~zandrawi/academic.htm
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