From: Christian Miller (milleschristian_at_yahoo.de)
Date: Wed Jan 10 2007 - 05:00:20 MST
For everybody who is interested:
It is really possible to translate VHDL to BLIF with
Altera Quartus II by enabling hidden variables in the
qsf-File of the project
(dumb_blif_before_optimize=true or
dump_blif_after_lut_map=true). But there are some
restrictions. You have to take care not to use FPGA
specific megafunctions (just take a device with no
megafunctions implemented, so i did with ALTERA MAX
II). Further BLIF cannot handle asyncronous signals,
in this case you have to rewrite your VHDL-code).
Best regards,
Christian Miller
University of Freiburg, Germany
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