From: yg2153_at_columbia.edu
Date: Mon Nov 27 2006 - 10:01:00 MST
Dear Sir/Madam
I am trying to verify a FSM i wrote for the controller of a 16 bit
processor. I tried verifying a small subset of the FSM which has
the same i/o signals but only has a few state transitions.
when I try to convert the file to blif_mv file the tool gives me a
message saying segmentation fault. It also generates the
corresponding .mv file but this file could not be read in vis where
it breaks with the error message unknown construct.
I ma attaching the controller file with this email.
I would be really gratefull for any help in this matter.
thanks
Yash
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