From: Fazela Vohra (fazela_at_gmail.com)
Date: Thu Jun 15 2006 - 10:10:41 MDT
Hello VIS Group,
I have a version of design compiler which does not support system verilog
format and hence I cannot synthesize many of the VIS benchmarks to flat
structural verilog
netlist. I would really appreciate if there would be a way to procure the
benchmarks in basic Verilog/VHDL format.
Thanks a lot,
Fazela
On 6/14/06, Fazela Vohra <fazela_at_gmail.com> wrote:
>
> Hello VIS group,
> I have a small question about the benchmarks that are available on the VIS
> site. I was trying to synthesize them using Synopsys Design Compiler but it
> complaints about the "typedef enum" statement that is used in the verilog
> description. I was just wondering if this is supported or I was doing
> something wrong on my side.
>
> Syntax error at or near token 'typedef'.
>
> Thanks a lot,
> Fazela
>
> --
> rock and pool is nice and cool.....so juicy fresh!
> our only wish is to catch a fish....so juicy freeeeshhh!
> -smeagol
>
-- rock and pool is nice and cool.....so juicy fresh! our only wish is to catch a fish....so juicy freeeeshhh! -smeagol
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