From: Flavio M. De Paula (depaulfm_at_cs.ubc.ca)
Date: Fri Jun 02 2006 - 23:05:38 MDT
This e-mail is in connection to the following e-mail, but it has more
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* Extra BDD nodes being created. Is this a bug? Flavio M. De Paula (Tue
May 30 2006 - 17:53:43 MDT)
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Hi fellow vis-users,
I expect the BDD generated by the command 'build_partition_mdds' (with no
options) to have nodes for inputs, present-state latches and next-state
latches -- or in terms of vis: primary-input, latch and shadow.
However, with the example attached to this message I noticed an extra node
being generated. Tracking it down in the blif-mv file, the bdd node is
related to a conditional branch (line 27 in comp.v).
At this point, I don't understand the reasoning for this extra node.
I would *really* appreciate any help on this. My best guess is that vl2mv
does generate bogus logic when a conditional branch is over two variables,
e.g (a == b), instead of a variable and a constant, e.g (a == 1).
Attached to this file you have the following:
1. the verilog file: comp.v
2. its blif-mv file: comp.mv
3. VIS output file: vis_output
You can search file vis_output for the string "<<<<<<<<<------ Extra Node"
Thank you,
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