bug about vl2mv

From: gepolv (sssssiqn_at_gmail.com)
Date: Wed May 10 2006 - 23:11:58 MDT


 I am sorry to bother you,but i think you are the first person in the world
to help me :) I am a graduate student and my major is FPGA CAD .So
,i used the tool vl2mv to translate verilog file to blif-mv file.But now ,i
encounter a big problem:the clock constraints information was not reflected
in the
final file(blif_mv file) which is really strange!
sourcefile dff.v:
module dff(q,d,c);
output q;
input d,c;
reg q;
always @(negedge c)
begin
q=d;
end
endmodule
the commend used is:
>read_verilog dff.v
>write_blif dffr.blif
then the result file :
  dffr.blif:
# This blif file and the encoding file that was written out with it cannot
# currently be read back into VIS. If you would like to read the blif and
# encoding files back into VIS, then use the 'write_blif -l' or
#'write_blif -c' options.
.model dff
.inputs d0
.outputs q0
.latch _n20 q0 2
.names d0 q$raw_n00
1 1
.names _n10
1
.names _n10 q$raw_n00 _n20
11 1
.exdc
.end

the result file does not include clock constraint information!
Any help will be great appreciated !

Gepo Lv



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