Re: Simulating verilog HDL using VIS

From: Mohammad.R Kakoee (kakoee_at_cad.ece.ut.ac.ir)
Date: Sun Apr 16 2006 - 23:47:16 MDT


Hi,
Please let me know which platform do you use? ( Unix / Windows)
and in which tool you are trying to build VIS?
( Visual C / ...)
I can guide you if I have this informqation.

> yytext is part of a parsing framework that uses the programs
> "yacc"/"lex" and/or "bison". make sure that you have the correct version
> and that these are in your path.
>
>
> On Sun, 2006-04-16 at 10:24 +0100, Kusum Lata wrote:
>> Hi all,
>>
>> I am also facing the same problem as Robert had,while building th
>> VIS.
>> and i am getting this message in the end,when it quit the make
>> script.
>>
>> ***************************************************************************
>> ./src/ctlp/ctlp.y: In function `int CtlpYyparse()':
>> ./src/ctlp/ctlp.y:296: error: `yytext' undeclared (first use this
>> function)
>> ./src/ctlp/ctlp.y:296: error: (Each undeclared identifier is reported
>> only once
>> for each function it appears in.)
>> make: *** [obj/ctlpRead.o] Error 1
>>
>> ***************************************************
>> and after that it stops.
>> Does anybody have any idea,why it is so and what i can do in this
>> case?
>> to build the VIS?
>> Thanks in advance
>>
>> Kusum
>>
>>
>>
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Mohammad.Reza kakoee
ECE Department, University of Tehran
http://cad.ece.ut.ac.ir/~kakoee



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