From: Andrew Burnside (Andrew.Burnside_at_sli-institute.ac.uk)
Date: Sat Nov 05 2005 - 02:35:31 MST
Hi
This doens't work yet, as I have problems with mapping the flip flops using vl2mv.
Sometimes I can get vl2mv to process the Verilog, but then fail at reading into vis.
Regards
Andrew
________________________________
From: owner-vis-users_at_lists.colorado.edu on behalf of Xingwen XU
Sent: Sat 05/11/2005 03:48
To: vis-users_at_lists.colorado.edu
Subject: RE: vl2mv
Hi, Andrew:
Your work will be great helpful to me (and maybe to other VIS users),
May you share your mapping scripts? Thank you so much.
________________________________
From: owner-vis-users_at_lists.colorado.edu [mailto:owner-vis-users_at_lists.colorado.edu] On Behalf Of Andrew Burnside
Sent: 2005?10?31? 5:50
To: vis-users_at_colorado.edu
Subject: vl2mv
Please can anyone tell me if vl2mv supports named ports in Verilog modules.
I am trying to produce a general process for producing suitable for producing Verilog suitable for input into vl2mv.
Verilog / SystemVerilog -> Synopysis DC -> vl2mv input
So far, I have produced a Synopsys technology library with basic AND / OR / INV / TRISTATE / FF mappings.
However, I am trying to debug some of the flip-flop behaviour. I am using multiple clock domains, so using the explicit clocking options on vl2mv.
Regards
Andrew
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