From: Prasad AVSS (avssp_gioe_at_yahoo.com)
Date: Sun Oct 30 2005 - 20:53:53 MST
Friends,
When I generated the blif for my verilog files usng VL2MV (2.1), it appears to be generating a truncated output file (round about 750 lines of output file). It doesn't give any warning message at the time of running. Is there any limit on the size of the file the VL2MV can handle.
Are there any switches that need to be enabled ?
Any help on this will be highly appreciated. I have also attached the source files for reference.
Rgds
Prasad
---------------------------------
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# vl2mv fpu.v
# version: 1.4
# date: 07:53:27 10/31/2005 (IST)
.model fpu_dec
# I/O ports
.outputs cyc1_rdy
.outputs opcode_look
.outputs fpu_state<0> fpu_state<1> fpu_state<2> fpu_state<3> fpu_state<4> fpu_state<5> fpu_state<6> fpu_state<7>
.inputs sin
.inputs sm
.inputs long_out
.outputs fpbusyn
.outputs so
.inputs valid_opcode
.outputs nx_opcode_look
.inputs int_out
.inputs fpuhold
.inputs two_cycle_in
.inputs reset_l
.inputs fpkill
.inputs mfinish
.inputs dp_out
# assign S0 = 'b00000001
.names _n1<0>
1
.names _n1<1>
0
.names _n1<2>
0
.names _n1<3>
0
.names _n1<4>
0
.names _n1<5>
0
.names _n1<6>
0
.names _n1<7>
0
.names _n1<0> S0$raw_n0<0>
- =_n1<0>
.names _n1<1> S0$raw_n0<1>
- =_n1<1>
.names _n1<2> S0$raw_n0<2>
- =_n1<2>
.names _n1<3> S0$raw_n0<3>
- =_n1<3>
.names _n1<4> S0$raw_n0<4>
- =_n1<4>
.names _n1<5> S0$raw_n0<5>
- =_n1<5>
.names _n1<6> S0$raw_n0<6>
- =_n1<6>
.names _n1<7> S0$raw_n0<7>
- =_n1<7>
# assign S1 = 'b00000010
.names _n3<0>
0
.names _n3<1>
1
.names _n3<2>
0
.names _n3<3>
0
.names _n3<4>
0
.names _n3<5>
0
.names _n3<6>
0
.names _n3<7>
0
.names _n3<0> S1$raw_n2<0>
- =_n3<0>
.names _n3<1> S1$raw_n2<1>
- =_n3<1>
.names _n3<2> S1$raw_n2<2>
- =_n3<2>
.names _n3<3> S1$raw_n2<3>
- =_n3<3>
.names _n3<4> S1$raw_n2<4>
- =_n3<4>
.names _n3<5> S1$raw_n2<5>
- =_n3<5>
.names _n3<6> S1$raw_n2<6>
- =_n3<6>
.names _n3<7> S1$raw_n2<7>
- =_n3<7>
# assign S2 = 'b00000100
.names _n5<0>
0
.names _n5<1>
0
.names _n5<2>
1
.names _n5<3>
0
.names _n5<4>
0
.names _n5<5>
0
.names _n5<6>
0
.names _n5<7>
0
.names _n5<0> S2$raw_n4<0>
- =_n5<0>
.names _n5<1> S2$raw_n4<1>
- =_n5<1>
.names _n5<2> S2$raw_n4<2>
- =_n5<2>
.names _n5<3> S2$raw_n4<3>
- =_n5<3>
.names _n5<4> S2$raw_n4<4>
- =_n5<4>
.names _n5<5> S2$raw_n4<5>
- =_n5<5>
.names _n5<6> S2$raw_n4<6>
- =_n5<6>
.names _n5<7> S2$raw_n4<7>
- =_n5<7>
# assign S3 = 'b00001000
.names _n7<0>
0
.names _n7<1>
0
.names _n7<2>
0
.names _n7<3>
1
.names _n7<4>
0
.names _n7<5>
0
.names _n7<6>
0
.names _n7<7>
0
.names _n7<0> S3$raw_n6<0>
- =_n7<0>
.names _n7<1> S3$raw_n6<1>
- =_n7<1>
.names _n7<2> S3$raw_n6<2>
- =_n7<2>
.names _n7<3> S3$raw_n6<3>
- =_n7<3>
.names _n7<4> S3$raw_n6<4>
- =_n7<4>
.names _n7<5> S3$raw_n6<5>
- =_n7<5>
.names _n7<6> S3$raw_n6<6>
- =_n7<6>
.names _n7<7> S3$raw_n6<7>
- =_n7<7>
# assign S4 = 'b00010000
.names _n9<0>
0
.names _n9<1>
0
.names _n9<2>
0
.names _n9<3>
0
.names _n9<4>
1
.names _n9<5>
0
.names _n9<6>
0
.names _n9<7>
0
.names _n9<0> S4$raw_n8<0>
- =_n9<0>
.names _n9<1> S4$raw_n8<1>
- =_n9<1>
.names _n9<2> S4$raw_n8<2>
- =_n9<2>
.names _n9<3> S4$raw_n8<3>
- =_n9<3>
.names _n9<4> S4$raw_n8<4>
- =_n9<4>
.names _n9<5> S4$raw_n8<5>
- =_n9<5>
.names _n9<6> S4$raw_n8<6>
- =_n9<6>
.names _n9<7> S4$raw_n8<7>
- =_n9<7>
# assign S5 = 'b00100000
.names _nb<0>
0
.names _nb<1>
0
.names _nb<2>
0
.names _nb<3>
0
.names _nb<4>
0
.names _nb<5>
1
.names _nb<6>
0
.names _nb<7>
0
.names _nb<0> S5$raw_na<0>
- =_nb<0>
.names _nb<1> S5$raw_na<1>
- =_nb<1>
.names _nb<2> S5$raw_na<2>
- =_nb<2>
.names _nb<3> S5$raw_na<3>
- =_nb<3>
.names _nb<4> S5$raw_na<4>
- =_nb<4>
.names _nb<5> S5$raw_na<5>
- =_nb<5>
.names _nb<6> S5$raw_na<6>
- =_nb<6>
.names _nb<7> S5$raw_na<7>
- =_nb<7>
# assign S6 = 'b01000000
.names _nd<0>
0
.names _nd<1>
0
.names _nd<2>
0
.names _nd<3>
0
.names _nd<4>
0
.names _nd<5>
0
.names _nd<6>
1
.names _nd<7>
0
.names _nd<0> S6$raw_nc<0>
- =_nd<0>
.names _nd<1> S6$raw_nc<1>
- =_nd<1>
.names _nd<2> S6$raw_nc<2>
- =_nd<2>
.names _nd<3> S6$raw_nc<3>
- =_nd<3>
.names _nd<4> S6$raw_nc<4>
- =_nd<4>
.names _nd<5> S6$raw_nc<5>
- =_nd<5>
.names _nd<6> S6$raw_nc<6>
- =_nd<6>
.names _nd<7> S6$raw_nc<7>
- =_nd<7>
# assign S7 = 'b10000000
.names _nf<0>
0
.names _nf<1>
0
.names _nf<2>
0
.names _nf<3>
0
.names _nf<4>
0
.names _nf<5>
0
.names _nf<6>
0
.names _nf<7>
1
.names _nf<0> S7$raw_ne<0>
- =_nf<0>
.names _nf<1> S7$raw_ne<1>
- =_nf<1>
.names _nf<2> S7$raw_ne<2>
- =_nf<2>
.names _nf<3> S7$raw_ne<3>
- =_nf<3>
.names _nf<4> S7$raw_ne<4>
- =_nf<4>
.names _nf<5> S7$raw_ne<5>
- =_nf<5>
.names _nf<6> S7$raw_ne<6>
- =_nf<6>
.names _nf<7> S7$raw_ne<7>
- =_nf<7>
.subckt mj_s_mux2_d_8 fpumux mx_out<0>=next_fpu_statep<0> mx_out<1>=next_fpu_statep<1> mx_out<2>=next_fpu_statep<2> mx_out<3>=next_fpu_statep<3> mx_out<4>=next_fpu_statep<4> mx_out<5>=next_fpu_statep<5> mx_out<6>=next_fpu_statep<6> mx_out<7>=next_fpu_statep<7> sel=fpkill in0<0>=next_fpu_state<0> in0<1>=next_fpu_state<1> in0<2>=next_fpu_state<2> in0<3>=next_fpu_state<3> in0<4>=next_fpu_state<4> in0<5>=next_fpu_state<5> in0<6>=next_fpu_state<6> in0<7>=next_fpu_state<7> in1<0>=S0<0> in1<1>=S0<1> in1<2>=S0<2> in1<3>=S0<3> in1<4>=S0<4> in1<5>=S0<5> in1<6>=S0<6> in1<7>=S0<7>
.names fpuhold _n10
0 1
1 0
.subckt mj_s_ff_snre_d_8 ff_fpstate out<0>=fpu_state<0> out<1>=fpu_state<1> out<2>=fpu_state<2> out<3>=fpu_state<3> out<4>=fpu_state<4> out<5>=fpu_state<5> out<6>=fpu_state<6> out<7>=fpu_state<7> din<0>=next_fpu_statep<0> din<1>=next_fpu_statep<1> din<2>=next_fpu_statep<2> din<3>=next_fpu_statep<3> din<4>=next_fpu_statep<4> din<5>=next_fpu_statep<5> din<6>=next_fpu_statep<6> din<7>=next_fpu_statep<7> lenable=_n10 reset_l=reset_l
.names _n11
1
.names _n11 fpu_state<0> _n14<0>
.def 0
0 1 1
1 0 1
.names _n14<0> _n15
.def 1
0 0
.names _n15 _n13
0 1
1 0
.names _n13 _n12
1 1
0 0
.names valid_opcode _n16
0 1
1 0
.names _n16 _n17
- =_n16
# next_fpu_state = S0
.names S0<0> next_fpu_state$_n16_n18$true<0>
- =S0<0>
.names S0<1> next_fpu_state$_n16_n18$true<1>
- =S0<1>
.names S0<2> next_fpu_state$_n16_n18$true<2>
- =S0<2>
.names S0<3> next_fpu_state$_n16_n18$true<3>
- =S0<3>
.names S0<4> next_fpu_state$_n16_n18$true<4>
- =S0<4>
.names S0<5> next_fpu_state$_n16_n18$true<5>
- =S0<5>
.names S0<6> next_fpu_state$_n16_n18$true<6>
- =S0<6>
.names S0<7> next_fpu_state$_n16_n18$true<7>
- =S0<7>
.names two_cycle_in _n19
- =two_cycle_in
# next_fpu_state = S1
.names S1<0> next_fpu_state$two_cycle_in_n1a$true<0>
- =S1<0>
.names S1<1> next_fpu_state$two_cycle_in_n1a$true<1>
- =S1<1>
.names S1<2> next_fpu_state$two_cycle_in_n1a$true<2>
- =S1<2>
.names S1<3> next_fpu_state$two_cycle_in_n1a$true<3>
- =S1<3>
.names S1<4> next_fpu_state$two_cycle_in_n1a$true<4>
- =S1<4>
.names S1<5> next_fpu_state$two_cycle_in_n1a$true<5>
- =S1<5>
.names S1<6> next_fpu_state$two_cycle_in_n1a$true<6>
- =S1<6>
.names S1<7> next_fpu_state$two_cycle_in_n1a$true<7>
- =S1<7>
# next_fpu_state = S2
.names S2<0> next_fpu_state$two_cycle_in_n1b$false<0>
- =S2<0>
.names S2<1> next_fpu_state$two_cycle_in_n1b$false<1>
- =S2<1>
.names S2<2> next_fpu_state$two_cycle_in_n1b$false<2>
- =S2<2>
.names S2<3> next_fpu_state$two_cycle_in_n1b$false<3>
- =S2<3>
.names S2<4> next_fpu_state$two_cycle_in_n1b$false<4>
- =S2<4>
.names S2<5> next_fpu_state$two_cycle_in_n1b$false<5>
- =S2<5>
.names S2<6> next_fpu_state$two_cycle_in_n1b$false<6>
- =S2<6>
.names S2<7> next_fpu_state$two_cycle_in_n1b$false<7>
- =S2<7>
# if/else (two_cycle_in )
.names next_fpu_state$two_cycle_in_n1a$true<0> next_fpu_state$two_cycle_in_n1b$false<0> two_cycle_in next_fpu_state$two_cycle_in$raw_n1d<0>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$two_cycle_in_n1a$true<1> next_fpu_state$two_cycle_in_n1b$false<1> two_cycle_in next_fpu_state$two_cycle_in$raw_n1d<1>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$two_cycle_in_n1a$true<2> next_fpu_state$two_cycle_in_n1b$false<2> two_cycle_in next_fpu_state$two_cycle_in$raw_n1d<2>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$two_cycle_in_n1a$true<3> next_fpu_state$two_cycle_in_n1b$false<3> two_cycle_in next_fpu_state$two_cycle_in$raw_n1d<3>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$two_cycle_in_n1a$true<4> next_fpu_state$two_cycle_in_n1b$false<4> two_cycle_in next_fpu_state$two_cycle_in$raw_n1d<4>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$two_cycle_in_n1a$true<5> next_fpu_state$two_cycle_in_n1b$false<5> two_cycle_in next_fpu_state$two_cycle_in$raw_n1d<5>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$two_cycle_in_n1a$true<6> next_fpu_state$two_cycle_in_n1b$false<6> two_cycle_in next_fpu_state$two_cycle_in$raw_n1d<6>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$two_cycle_in_n1a$true<7> next_fpu_state$two_cycle_in_n1b$false<7> two_cycle_in next_fpu_state$two_cycle_in$raw_n1d<7>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
# if/else (!valid_opcode )
.names next_fpu_state$_n16_n18$true<0> next_fpu_state$two_cycle_in$raw_n1d<0> _n16 next_fpu_state$_n16$raw_n29<0>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$_n16_n18$true<1> next_fpu_state$two_cycle_in$raw_n1d<1> _n16 next_fpu_state$_n16$raw_n29<1>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$_n16_n18$true<2> next_fpu_state$two_cycle_in$raw_n1d<2> _n16 next_fpu_state$_n16$raw_n29<2>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$_n16_n18$true<3> next_fpu_state$two_cycle_in$raw_n1d<3> _n16 next_fpu_state$_n16$raw_n29<3>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$_n16_n18$true<4> next_fpu_state$two_cycle_in$raw_n1d<4> _n16 next_fpu_state$_n16$raw_n29<4>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$_n16_n18$true<5> next_fpu_state$two_cycle_in$raw_n1d<5> _n16 next_fpu_state$_n16$raw_n29<5>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$_n16_n18$true<6> next_fpu_state$two_cycle_in$raw_n1d<6> _n16 next_fpu_state$_n16$raw_n29<6>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names next_fpu_state$_n16_n18$true<7> next_fpu_state$two_cycle_in$raw_n1d<7> _n16 next_fpu_state$_n16$raw_n29<7>
0 - 1 0
1 - 1 1
- 0 0 0
- 1 0 1
.names _n11 fpu_state<1> _n36<1>
.def 0
0 1 1
1 0 1
.names _n36<1> _n37
.def 1
0 0
.names _n37 _n35
0 1
1 0
.names _n35 _n34
1 1
0 0
# next_fpu_state = S2
.names S2<0> next_fpu_state$_n34_n38$true<0>
- =S2<0>
.names S2<1> next_fpu_state$_n34_n38$true<1>
- =S2<1>
.names S2<2> next_fpu_state$_n34_n38$true<2>
- =S2<2>
.names S2<3> next_fpu_state$_n34_n38$true<3>
- =S2<3>
.names S2<4> next_fpu_state$_n34_n38$true<4>
- =S2<4>
.names S2<5> next_fpu_state$_n34_n38$true<5>
- =S2<5>
.names S2<6> next_fpu_state$_n34_n38$true<6>
- =S2<6>
.names S2<7> next_fpu_state$_n34_n38$true<7>
- =S2<7>
.names _n11 fpu_state<2> _n3b<2>
.def 0
0 1 1
1 0 1
.names _n3b<2> _n3c
.def 1
0 0
.names _n3c _n3a
0 1
1 0
.names _n3a _n39
1 1
0 0
# mfinish && long_out
.names mfinish long_out _n3d
.def 0
1 1 1
.names _n3d _n3e
- =_n3d
# next_fpu_state = S6
.names S6<0> next_fpu_state$_n3d_n3f$true<0>
- =S6<0>
.names S6<1> next_fpu_state$_n3d_n3f$true<1>
- =S6<1>
.names S6<2> next_fpu_state$_n3d_n3f$true<2>
- =S6<2>
.names S6<3> next_fpu_state$_n3d_n3f$true<3>
- =S6<3>
.names S6<4> next_fpu_state$_n3d_n3f$true<4>
- =S6<4>
.names S6<5> next_fpu_state$_n3d_n3f$true<5>
- =S6<5>
.names S6<6> next_fpu_state$_n3d_n3f$true<6>
- =S6<6>
.names S6<7> next_fpu_state$_n3d_n3f$true<7>
- =S6<7>
# mfinish && int_out
.names mfinish int_out _n40
.def 0
1 1 1
.names _n40 _n41
- =_n40
# next_fpu_state = S7
.names S7<0> next_fpu_state$_n40_n42$true<0>
- =S7<0>
.names S7<1> next_fpu_state$_n40_n42$true<1>
- =S7<1>
.names S7<2> next_fpu_state$_n40_n42$true<2>
- =S7<2>
.names S7<3> next_fpu_state$_n40_n42$true<3>
- =S7<3>
.names S7<4> next_fpu_state$_n40_n42$true<4>
- =S7<4>
.names S7<5> next_fpu_state$_n40_n42$true<5>
- =S7<5>
.names S7<6> next_fpu_state$_n40_n42$true<6>
- =S7<6>
.names S7<
/****************************************************************
---------------------------------------------------------------
Copyright 1999 Sun Microsystems, Inc., 901 San Antonio
Road, Palo Alto, CA 94303, U.S.A. All Rights Reserved.
The contents of this file are subject to the current
version of the Sun Community Source License, picoJava-II
Core ("the License"). You may not use this file except
in compliance with the License. You may obtain a copy
of the License by searching for "Sun Community Source
License" on the World Wide Web at http://www.sun.com.
See the License for the rights, obligations, and
limitations governing use of the contents of this file.
Sun, Sun Microsystems, the Sun logo, and all Sun-based
trademarks and logos, Java, picoJava, and all Java-based
trademarks and logos are trademarks or registered trademarks
of Sun Microsystems, Inc. in the United States and other
countries.
----------------------------------------------------------------
******************************************************************/
`define FADD 8'h62
`define DADD 8'h63
`define FSUB 8'h66
`define DSUB 8'h67
`define FMUL 8'h6a
`define DMUL 8'h6b
`define FDIV 8'h6e
`define DDIV 8'h6f
`define FREM 8'h72
`define DREM 8'h73
`define I2F 8'h86
`define I2D 8'h87
`define L2F 8'h89
`define L2D 8'h8a
`define F2I 8'h8b
`define F2L 8'h8c
`define D2I 8'h8e
`define D2L 8'h8f
`define F2D 8'h8d
`define D2F 8'h90
`define FCMPG 8'h96
`define FCMPL 8'h95
`define DCMPG 8'h98
`define DCMPL 8'h97
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