From: Andrew Burnside (Andrew.Burnside_at_sli-institute.ac.uk)
Date: Sun Oct 30 2005 - 13:49:32 MST
Please can anyone tell me if vl2mv supports named ports in Verilog modules.
I am trying to produce a general process for producing suitable for producing Verilog suitable for input into vl2mv.
Verilog / SystemVerilog -> Synopysis DC -> vl2mv input
So far, I have produced a Synopsys technology library with basic AND / OR / INV / TRISTATE / FF mappings.
However, I am trying to debug some of the flip-flop behaviour. I am using multiple clock domains, so using the explicit clocking options on vl2mv.
Regards
Andrew
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