From: Adnan Aziz (adnan_at_ece.utexas.edu)
Date: Thu Jun 23 2005 - 14:18:12 MDT
a couple of practical suggestions for experimenting with orderings:
- use write_order to get a file with an ordering, then tinker
with that file (just move lines around - only the first field in a line
is relevant, the rest is basically comments)
- try to look for variables that "differentiate" the input, e.g., control
bits for an ALU, and put them on top
- dynamic ordering is not the solution to all problems, can often
get stuck in local minima (e.g., if you don't bind present state
and next state variables, it will never figure out to do this,
and your substitute step in image computation will kill you.)
still it may give you some ideas of what a good ordering is.
if you want to learn more about the theory of orderings, read ken
mcmillan's phd thesis, also wegener's book
(http://www.amazon.com/exec/obidos/tg/detail/-/0898714583/qid=1119557788/sr=8-1/ref=sr_8_xs_ap_i1_xgl14/102-9656387-2368934?v=glance&s=books&n=507846)
bear in mind these results are for combinational functions and the reached
state set BDDs are a lot harder to figure out.
cheers,
adnan
-------------------------------------------
Adnan Aziz, Dept. of Elect. and Comp. Eng.,
The University of Texas, Austin TX, 78712
1 (512) 475-9774 www.ece.utexas.edu/~adnan
-------------------------------------------
On Wed, 22 Jun 2005, Rajsekhar Adapa wrote:
> Hello VIS Users
>
>
> I have Netlists of few Circuits in HDL format. I want to find a good
> variable ordering for forming the BDDs and ZDDs in the circuit. Can
> any one help me in suggesting which algorithm to use for finding a
> good varaible order for the inputs. It would be great you cite the
> Paper's Title which states the algorithm. Thanks for the help.
>
> Regards
> Raj
>
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