From: Fabio Somenzi (Fabio_at_colorado.edu)
Date: Sat May 07 2005 - 08:19:08 MDT
I second tun li's recommendation. In a pinch, you could use the simulation
command in vis, but if you are mostly interested in simulation, rather
than model checking, you'll be much better off with something like
>>>>> "t" == <tunlee_at_hotmail.com> writes:
t> Icarus Verilog is a open source Verilog simulator with rich functions. You can get it from:
t> tun li
t> ----- Original Message -----
t> From: "Robert" <mrhonest2000_at_yahoo.com>
t> To: <vis-users_at_lists.colorado.edu>
t> Sent: Saturday, May 07, 2005 2:09 PM
t> Subject: Simulating verilog HDL using VIS
>> I am looking for a cheap HDL simulator that I can use
>> to simulate my design.
>> Can VIS do this for me?
>> Do you Yahoo!?
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