Verilog to dot

From: Zaher S Andraus (zandrawi_at_eecs.umich.edu)
Date: Tue Oct 26 2004 - 19:18:04 MDT

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Hi folks,

I need to get an explicit representation of an FSM that
is exatrcted from Verilog. I found that VIS internal interface
can convert an "Automaton" into dot format. Does anyone
know how to build the Automaton from Verilog, or preferrably
whether I can get the Verilog to Dot externally without
using the internal interface?

Thanks in advance,
-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x
Zaher S. Andraus
Advanced Computer Architecture Laboratory in EECS
University of Michigan - Ann Arbor
http://www.eecs.umich.edu/~zandrawi/academic.htm
-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x

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