From: Charles Thangaraj (charles_at_engr.colostate.edu)
Date: Mon Jun 21 2004 - 11:55:53 MDT
There is a way to convert a VHDL file to a VERILOG file. Once you have done
this you can use VIS with the resulting Verilog file.
This is the link where you can get more info on the conversion.
>===== Original Message From vis-users_at_lists.colorado.edu =====
>I'm an italian student and I need to translate a vhdl source into blif (to
>check with vis) for my thesis.
>I know that vis doesn't accept vhdl source and so I'm looking for a vhdl to
blif translator (for linux).
>Can we help me? Does exist another method?
>Thanks in advance,
----------"A man who cannot laugh at himself is a fool"----------
Graduate Research Assistant,
VLSI System Architecture Lab,
Colorado State University.
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