From: David Howland (metalliqaz_at_fastmail.fm)
Date: Thu Jun 03 2004 - 20:39:32 MDT
yes, I have also tried the blocking assignment, no luck there either.
I assume it has something to do with the way that vl2mv generates the MV
code.
I guess I was assuming that there was a command that could resolve this kind
of issue, since I imagine that someone had to have experienced it before.
thank you for your generous help Fabio.
-dh
----- Original Message -----
From: "Fabio Somenzi" <Fabio_at_Colorado.EDU>
To: <vis-users_at_lists.colorado.edu>
Sent: Thursday, June 03, 2004 7:18 PM
Subject: Re: dump to blif
> >>>>> "m" == metalliqaz <metalliqaz_at_fastmail.fm> writes:
>
> m> verilog doesn't require the registers to be initialized,
>
> true, but vis does
>
> m> but I added this to the code in an attempt to fix the error:
>
> m> initial sum <= 0;
>
> m> no luck
>
> Change it to
>
> initial sum = 0;
>
>
> Fabio
>
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