From: Fabio Somenzi (Fabio_at_colorado.edu)
Date: Thu Jun 03 2004 - 17:18:03 MDT
>>>>> "m" == metalliqaz <metalliqaz_at_fastmail.fm> writes:
m> verilog doesn't require the registers to be initialized,
true, but vis does
m> but I added this to the code in an attempt to fix the error:
m> initial sum <= 0;
m> no luck
Change it to
initial sum = 0;
Fabio
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