From: metalliqaz_at_fastmail.fm
Date: Thu Jun 03 2004 - 17:06:19 MDT
verilog doesn't require the registers to be initialized, but I added this
to the code in an attempt to fix the error:
initial sum <= 0;
no luck
-dh
On Thu, 3 Jun 2004 15:44:44 -0600, "Fabio Somenzi" <Fabio_at_Colorado.EDU>
said:
> What's sum<1>'s initial value?
>
> >>>>> "m" == metalliqaz <metalliqaz_at_fastmail.fm> writes:
>
> m> Hi, I'm trying to dump a design from vis-2.0 to .blif format.
> m> vis refuses to do it, and gives me this output:
>
> vis> write_blif -R
> m> Latch sum<1> has a non-constant reset value - quitting.
>
> m> The only design for which I have been successful is a design that
> m> contained no registers at all.
> m> any help would be greatly appreciated!
> m> thanks,
> m> -dh
>
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