compilation problem, and 2 general questions

From: Zaher S Andraus (zandrawi_at_eecs.umich.edu)
Date: Sun Apr 11 2004 - 23:07:31 MDT

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Hi,

I get the following problem when trying to load the attached
Verilog code:
Error: Variable impl_mem<2> is not defined as an output of a table in
model top.

But impl_mem[2] is not accessed or defined in the code.
Impl_mem is a 2D array [1:0] (2 words), each is of width 32 bits.

vl2mv runs smoothly, and correctly defines the bahvior of impl_mem[0]
and impl_mem[1].
I can't figure out what the problem is.

Also, a general question: Is there anyway I can *check equivalence*
of 2 memory arrays, without explicitly checking equivalence
of each 2 correspondent words in the 2 arrays? (i.e. look
at the end of the file, signal 'eq').

Also, is there any way I can *initialize* a 2D array
non-deterministically, i.e. I dont care what the initial
value in all words is, and whether they are different
or not. How can I do that? What I know about VIS is that
"inputs" are treated as having non-deterministic value
each cycle, but 2D arrays can't be passed via module argument
in Verilog.

Thanks in advance,
-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x
Zaher S. Andraus
Advanced Computer Architecture Laboratory in EECS
University of Michigan - Ann Arbor
http://www.eecs.umich.edu/~zandrawi/academic.htm
-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x

• TEXT/PLAIN attachment: pipelined_xor_for_vis_flattened.v

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