simple front-end bug

From: Gordon Zhang (gordon_at_visc.vt.edu)
Date: Fri Apr 09 2004 - 13:10:56 MDT

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Hi There,

I have encountered a simple error with VIS, when using OFF-SET to
specify the logic gates.

test.blif:, which uses OFF-SET to speify an inverter.

.model top
.inputs a
.outputs b
.names a b
1 0

The VIS executes as :

vis> rl test.blif; flt; pns
 top combinational=1 pi=1 po=1 latches=0 pseudo=0 const=1 edges=0

Note that VIS says the gate is "constant". However, using "On-Set" in
specifying inverter does not produce the same error.

It appears that the "constant flag" of NtkNodeStruct for this gate was
erroneously set to true so that function Ntk_NodeTestIsConstant(
Ntk_Node_t * node), which is in returns TRUE for the gate.

Thanks

Gordon

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