From: Cedric Roux (Cedric.Roux_at_lip6.fr)
Date: Fri Apr 09 2004 - 04:08:28 MDT
Hi,
it is an internal variable of the file pipelined_xor_for_vis.mv
which is produced with vl2vm.
It comes from the line :
.latch _n24c<*1*><15> DataMem<*1*><15>
which means there is a problem with the construct:
reg [31:0] DataMem[1:0];
in the module spec if your verilog file.
I don't know much more about verilog, so I can't help you more.
You should use the command vl2vm and take a look at the .mv
file produced to trace the problem. Maybe some legal verilog
constructs that you use are not supported by vis ?
My 0.2 euros.
Cedric.
On Thu, 8 Apr 2004, Zaher S Andraus wrote:
>
> Hi,
>
> I am trying to use VIS for invariant checking.
> I get the following error message:
>
> vis> read_verilog pipelined_xor_for_vis.v
> pipelined_xor_for_vis.v
> Error: Variable _n24c<*1*><15> is not defined as an output of a table in
> model spec.
>
> And I can't figure out what _n24c is. The verilog file I am trying
> to compile is attached. Can anyone tell me where the problem is?
>
> Thanks,
> -x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x
> Zaher S. Andraus
> Advanced Computer Architecture Laboratory in EECS
> University of Michigan - Ann Arbor
> http://www.eecs.umich.edu/~zandrawi/academic.htm
> -x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x
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