From: Cedric Roux (Cedric.Roux_at_lip6.fr)
Date: Tue Jan 20 2004 - 07:19:17 MST
Dear vis community,
I have a problem with the "simulate" command.
Let's take this very simple program:
-----------------------------------------
typedef enum {A, B} state;
module main(clk, i);
input clk;
input i;
state reg s;
initial
begin
s = A;
end
always@(posedge clk)
begin
case (s)
A : s = B;
B : s = A;
endcase
end
endmodule
------------------------
It is a very simple fsm with 2 states, A and B.
We have:
A -> B
B -> A
The input is not used, but is there for the simulation
(in fact I have bigger examples, but I prefer to give this
simple one, because the problem appears even with it).
I do:
vl2mv test.v
Then I run vis (2.0).
read_blif_mv test.mv
flatten_hierarchy
static_order
build_partition_mdds
then I generate a simple simulation file:
simulate -n 1 -o test.sim
I edit it by hand to have this :
---------------------------------------
# vis release 2.0 (compiled 15-Dec-03 at 5:48 PM)
# Network: main
# Simulation vectors have been randomly generated
.inputs i
.latches s
.outputs
.initial A
.start_vectors
0
-------------------------
Then I do another simulation in vis:
simulate -i test.sim
And here is what I get:
-------------------------
# vis release 2.0 (compiled 15-Dec-03 at 5:48 PM)
# Network: main
# Input Vectors File: test.sim
.inputs i
.latches s
.outputs
.initial A
.start_vectors
# i ; s ;
0 ; A ;
# Final State : A
-----------------------------
My problem is that final state should be B, not A.
The documentation (help simulate), gives an example where the
final state is "green", which implicates that here the
answer should be "B" not "A". So what do I do wrong ?
I run vis with a intel pc with linux (something like a redhat) box.
Thank you for your help.
Cédric.
This archive was generated by hypermail 2.1.7 : Tue Jan 20 2004 - 07:22:32 MST