From: Chao Wang (Wangc_at_colorado.edu)
Date: Wed Nov 05 2003 - 01:42:39 MST
Fang,
I didn't why that's a problem -- you can define d0 as an array (in
verilog), and assign each bit $ND(0,1):
wire[0:15] d0;
assign d0[0] = $ND(0,1);
assign d0[1] = $ND(0,1);
...
Is that want you want?
Chao
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