/*  2-Bit Counter */

module counter(clk);

input  clk;

reg[0:1] state;

initial  state = 2'b00;

always @(posedge clk) 
begin
 case(state)
   2'b00:
	begin
 		state = 2'b10;
 	end

	2'b10:
	 begin
		state = 2'b01;
	 end

	2'b01:
	 begin
	 	state = 2'b11;
	 end

	2'b11:
	 begin
		state = 2'b00;
	 end

 endcase
end
endmodule