Fabio,
On Wed, 13 Mar 2002, Fabio Somenzi wrote:
> Hess,
>
> >>>>> "HH" == Hess Hodge <hhodge@cray.com> writes:
>
> HH> Hello,
> HH> First, here is some background: I'm using VIS-1.4, and I'm using synopsys
> HH> and edif2blif to create a blif file from verilog.
>
>
> HH> Here are a few VIS questions for you:
>
> HH> 1) Once I read in the design, I notice that there are a number of
> HH> pseudo-inputs associated with my registers, their names end in $INIT. So,
> HH> these pseudo-inputs are there to model nondeterminism on the initial-state
> HH> of these registers, right? How can I set these registers to a known
> HH> initial-state?
>
> Do you have an "initial" statement in your verilog description? I
> don't know exactly what the synopsys edif filter will do to such an
> initial statement, but that would be the first thing to look at.
Yes, I tried it with both an "initial" statement in the verilog, and
without. Apparently synopsys ignores the initial values when writing the
edif file.
According to the "ntk" package documentation, the pseudo-input takes on
values from a table. Is there any way to manipulate this table to
effectively set a specific initial state for the design?
Regards,
Hess
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