Hello,
First, here is some background: I'm using VIS-1.4, and I'm using synopsys
and edif2blif to create a blif file from verilog.
Here are a few VIS questions for you:
1) Once I read in the design, I notice that there are a number of
pseudo-inputs associated with my registers, their names end in $INIT. So,
these pseudo-inputs are there to model nondeterminism on the initial-state
of these registers, right? How can I set these registers to a known
initial-state?
2) I also have a number of primary-inputs in my design. When I check my
design I want to place a constraint on the inputs. Say, for example, I
want to constrain inputs A and B so that it is never the case that
both are set, ie !(A=1 * B=1). Is there a way to constrain the inputs?
3) My verilog design has a clock input called "Lclk". I translate
the verilog to edif and then to blif. The resulting blif file has a
number of .latch statements like the following:
.latch i_reset reset_reg re Lclk 2
(input = i_reset, output = reset_reg, and it is clocked on the rising edge
of Lclk, with an initial value of "dont care")
Then, when I read this blif file into VIS, I get the following warning:
vis> read_blif -v csi_inbound_ctrl.blif
Warning: Variable Lclk is not used in csi_inbound_ctrl.
Has my Lclk been abstracted out of the design at this point? Do I need to
edit my blif file to include a .clock statement?
Thanks!
Hess Hodge
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