Hi Vanessa,
In case you haven't found the answer yet....
I believe the problem that you're having resides in the following
segment of your code:
always@(posedge clk or negedge rst)
if(!rst) state <= #1 grant0;
else state <= #1 next_state;
vl2mv doesn't handle well non-blocking assignments. I would suggest you
to modify to blocking assignment. vl2mv will synthesize the state as a
flip-flop.
Another problem in this code is that you should use "initial" statement
for initialization purposes. vl2mv doesn't handle assynchronous reset.
The VIS documentation covers these cases.
Have fun! :-)
Flavio,
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