Hi I have the following verilog description:
module test(a, b, sel, out);
input a, b, sel;
output out;
wire a, b, sel;
wire out;
assign out = (sel) ? a : b;
endmodule
I want to convert the verilog format to .mv with 'vl2mv.lin71' but I got
the following error message:
parse error : (line:1;file:test.v) token :'module', yacc token : 'module'
am I missing something?
Thank You,
Codrin.
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