Vanessa,
Asynchronous signals are a problem. You'll have to
make the circuit synchronous and take into account
some imprecision.
Below is a suggestion, in which reset is only
accounted for at the next clock tick. Notice that
this is OK for vis; vis cannot look `between' clock
ticks.
module main(clk,in,load,rs,out);
input in,rs,load,clk;
output out;
wire[2:0] in;
reg[2:0] out;
reg oldrs;
always @(posedge clk) begin
if(rs & ~oldrs) //posedge rs
out=0;
else if(load)
out=in;
else
out = out + 1;
oldrs = rs;
end
endmodul
--- vanessa goyal <vanessa_goyal@rediffmail.com>
wrote:
>
> Sir,
>
> For the code below,Vl2mv is showing
> translation may be imprecise.
>
> How should I modify it,so that Vl2mv can accept it?
>
> Thanking You
> Vanessa
> *************************************
> module main(clk,in,load,rs,out);
> input in,rs,load,clk;
> output out;
> wire[2:0] in;
> reg[2:0] out;
>
> always @(posedge clk or posedge r )
> begin
> if(rs) out=0; else if(load) out=in; else out = out +
> 1;
> end
> endmodule
>
>
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