Sir,
For the code below,Vl2mv is showing
translation may be imprecise.
How should I modify it,so that Vl2mv can accept it?
Thanking You
Vanessa
*************************************
module main(clk,in,load,rs,out);
input in,rs,load,clk;
output out;
wire[2:0] in;
reg[2:0] out;
always @(posedge clk or posedge r )
begin
if(rs) out=0; else if(load) out=in; else out = out + 1;
end
endmodule
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