Vanessa,
You are assigning two different things to add at the
same time: when the clock goes high and loadl is high,
on the one hand you say that add becomes 5, on the
other hand you say that it should be increased by one.
Which is it? This leads to a nondeterministic table,
which is not allowed in vis.
You cannot mix positive and negative clock edges. One
solution is to create an explicit clock: a register c
that flips at every clock tick. (always @clock c =
~c.) Then you can prefix things that have to happen
at the negative edge by "if ~c", and those that happen
at the positive edge by "if c".
Roderick
--- vanessa goyal <vanessa_goyal@rediffmail.com>
wrote:
>
> Sir,
> For the following code while operating "INIT"
> command,
> error coming is "cannot perform flatten herarchy.
> Please tell me what's the problem with the code?
>
> VIS supports using both posedge and negedge in the
> same code or not?
>
*******************************************************momodule
> main(clk,load,add,sub);
> input load,clk;
> output add,sub;
> wire load,clk;
> reg loadl;
> reg[3:0] add,sub;
>
> initial begin add=0;sub=0;end
>
> always@ (posedge clk)
> begin
> loadl=load;
> end
>
> always@ (posedge clk)
> begin
> if(loadl) begin add=5;sub=5;end
> end
>
> always@ (posedge clk)
> begin
> add=add+1;
> sub=sub-1;
> end
>
> endmodule
>
> Thanking you
> Vanessa
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