Language Emptiness

From: Fabio Somenzi (Fabio@colorado.edu)
Date: Mon Sep 24 2001 - 11:54:03 MDT

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Have you checked the section "Formal Verification in VIS" of the
User's Manual?

Also, see http://vlsi.colorado.edu/~vis/vis-users/0181.html

>>>>> "vg" == vanessa goyal <vanessa_goyal@rediffmail.com> writes:

vg> Hello Sir,

vg> There's no any example or details are provided on VIS site which
vg> deals with language emptiness.

vg> Please give me an idea about ,in which type of verilog
vg> designs(practical hardware design) emptiness checking is
vg> required,and how can we do it by VIS(command script).

vg> Thanking you
vg> Vanessa

-- 
Fabio Somenzi          | Phone: 303-492-3466
University of Colorado | Fax:   303-492-2758
ECE Dept.              | Email: Fabio@Colorado.EDU
Boulder CO 80309-0425  | WWW:   http://vlsi.colorado.edu/~fabio

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